This disclosure related to electronic design automation (EDA), more particularly to techniques for topological routing of semiconductor packages.
A System-in-a-Package or System in Package (SiP) can include a number of integrated circuits or chips enclosed in a single package or module. SiP with more than one microchip in a package can improve performance and reduce costs. SiP may perform all or most of the functions of an electronic system, such as used inside a mobile phone, PC, digital music player, etc. Compared with system-on-a-chip (SOC), SiP may provide higher integration, greater flexibility, and faster time to market and is becoming a mainstream technology.
SIP usually uses ball grid array (BGA) substrate and wire bonding or flip-chip to connect a microchip to a substrate. Compared with earlier dual-in-line packages (DIPs) and pin grid array (PGA) packages, BGA can have higher integrity, higher reliability, lower coupling, reduced cost, and lower thermal-resistance solder balls. With SiP, silicon dies containing chips may be stacked vertically on the BGA substrate, and may be internally connected by fine wires that are buried in the package. Alternatively, with a flip chip technology, solder bumps can be used to join stacked chips together.
For wire bonding dies, I/O pads of a microchip may be connected to bond pads around the chip cavity through bonding wires. For flip-chip dies, on-chip re-distribution layer (RDL) routing may first connect I/O pads to bump pads. Escape routing may then break out bump pads to the boundary of the die (i.e., the escape break points) in build-up or signal layers associated with the package. Off-chip substrate routing may connect escape break points of flip-chip dies or bond pads of wire bonding dies to balls (usually in the bottom layer) of a BGA package substrate. However, high-density SiP integration makes off-chip routing a challenging task. Some design challenges include high-density, planar, and non-Manhattan requirements. Additionally, existing substrate routing may allow limited locations for start-points.
Off-chip substrate routing usually includes two steps: topological routing and detailed routing. In general, the escape break point for a flip-chip or the bond pad for a wire bonding die can be called a start-point, and the location above the center of the corresponding ball (but in the same layer as the start-point) can be called its end-point. After topological routing, staggered vias may be used to connect an end-point to a ball of a BGA package.
Many attempts at topological routing can be called 1.5 D (one and a half dimensional) routing. In general, the build-up layer may be divided into four zones. In every zone, all bond-pads can be located in one line. Often, bond-pads may be assumed to be located along a single rectangular ring. Pins may then be located side to side with respect to the bond-pads. However, SiP can require flexible locations of bond-pads and escape break points beyond the single rectangular ring. Therefore, conventional 1.5 D routing may not be flexible enough for SiP and even some one-die packages. Moreover, once a net is routed, it can become an obstacle for other un-routed nets and may impact the results of routing, resulting in the net ordering problem.
Accordingly, what is desired is to solve problems relating to topological routing of semiconductor packages, some of which may be discussed herein. Additionally, what is desired is to reduce drawbacks related to topological routing of semiconductor packages, some of which may be discussed herein.